A typical RF (Radio Frequency) CMOS (Complementary Metal-Oxide-Semiconductor) transistor comprises a comb arrangement of narrow metal lines (also referred to as ‘fingers’) which connect up the source and drain terminals. Such multi-finger designs were originally developed for technologies which used interconnect comprising aluminium metal layers and tungsten vias and these designs were motivated by the limited number of available interconnect levels, material properties and processing considerations (e.g. the resistance of vias and problems associated with hydrogen gettering). More recently, with the improvement in processing technologies, there has been a change to copper interconnect, a transition to shorter gate length and a reduction in gate-oxide thicknesses. While sealing the gate length significantly enhances the switching speed of the transistor channel, the series resistances of the gate electrode as well as the source and drain increase, limiting the performance gain and deteriorating the noise performance. To mitigate these effects the conventional layout has been modified to include more gate-fingers, with reduced width of the channel width in order to maintain the same overall device width and drive current. Additionally, the layout has been modified to include connections to the gate at both ends.
FIG. 1 is a schematic diagram of a RE CMOS transistor design which shows only a subset of the CMOS layers: active area (also referred to as ‘active’) 102, gate electrode (also referred to as ‘poly’, nevertheless the gate electrode may consist of other materials than poly-silicon) 104, metal-1 106 and metal-2 108. In this example, the metal fingers 110 are formed in the metal-2 layer 108 directly above metal-1 (not shown) and the fingers connecting to the source and drain terminals 112, 114 are interleaved. The metal-1 layer 106 provides a gate strap comprising a metal ring 116 around the perimeter of the device.
Use of narrower metal connection lines (where the connection width is indicated by arrow 121), however, results in a reduction in the current carrying capability of the source and drain connections (as limited by electromigration criteria) and also results in an increase in the series resistance of these connections (which results in a voltage drop along the finger connections).
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known RF CMOS transistors and transistor designs.